Signoff-Driven Timing Closure ECO in the Synopsys Galaxy Platform

The adoption of a predictable ECO flow that eliminates violations in all signoff scenarios without inadvertently introducing new ones helps reduce the number of timing iterations required for final signoff. Static timing analysis tools provide predictable, signoff-accurate guidance to implementation tools with the following capabilities: ` ` Fix design rule constraint (DRC), setup, and hold violations without creating new violations (therefore preventing a “ping pong” effect). ` ` Perform pessimism reduction techniques such as advanced on-chip variation (AOCV), parametric onchip variation (POCV), and path-based analysis (PBA) across all scenarios. ` ` Consider physical design information to achieve best quality of results (QoR) and reduce major perturbations for designs already placed and routed.